1. Field of the Invention
The present invention generally relates to a manufacturing method of a circuit board, and in particular to a manufacturing method of a non-etched circuit board.
2. The Prior Arts
Since the trend toward small and light weight for electronic products as well as continuous enhancement of function, I/O ports of semiconductor chips are increased rapidly, and accordingly, chip packaging technologies are continuously undated. Nowadays in high-end IC products, the Flip-Chip technology has been adopted to squeeze numerous electrical connections into a small package.
Conventionally, a build up material, such as fiberglass prepreg, is applied to manufacture a fine line with a pitch of 50 μm. A copper foil with a thickness of 1.5-5.0 μm is used as a conductive plating pattern layer, and finally, the copper foil is etched with flash etching. As the copper foil needs to have a rough surface to couple with the glass prepreg, the etching amount on the copper foil has to be further increased. That causes the line width not to be further reduced after electroplated. Since the etching amount, due to the limitation on the thickness of the copper foil, cannot be reduced, the conventional method cannot manufacture the high-density fine line circuit board with a pitch below 50 μm.
Generally, when electroplating nickel/gold on a circuit layer of a packaging substrate, an electrical current needs to be transmitted into the substrate, particularly into the circuit layer for electroplating via a conductive line connected to the circuit layer. Although the electroplated nickel/gold layer can entirely cover the circuit layer, the conductive lines will still remain in the circuit board, which occupies the circuit board and thus reduces the wiring area. To solve the problem, the conductive lines have to be narrowed down. But this will result in a non-uniform thickness of the electroplated nickel/gold layer. Therefore, to narrow down the conductive lines is not a good way to increase the wiring density.
To enhance conductivity, reduce noise and increase wiring density, the design of NPL (non-plating line) was provided, which has no need to plate the lines on the surface of the circuit board. However, the wire bonding area still adopts the nickel/gold electroplating for better adherence. The wire bonding area may also adopt a chemical nickel/gold, but its reliability is relatively poor. Therefore, the GPP (gold pattern plating) process is usually used for manufacturing the circuit boards with the design of NPL, whose wire bonding area adopts the nickel/gold electroplating.
However, before performing the GPP process, since the electroplated nickel/gold layer is formed prior to the solder mask (SM) layer, the electroplated nickel/gold layer has a larger area than the SM layer. Besides, the SM layer and the electroplated nickel/gold layer have a worse adherence to each other; thereby, it does not meet with the demands of high reliability and heat resistance.
Except that the non-plating line (NPL) process is highly complex, special machines are required in electroplating a copper foil, and it is difficult to control the etching parameters after copper electroplating. These will result in a micro short during the reliability test, and thus an irretrievable loss.
No matter what kinds of non-plating line (NPL) processes, it still needs to perform a selective etching on a metal layer and define a non-etched metal layer as a circuit layer. However, in the current etching technologies, the etching processes are difficult to be precisely controlled; accordingly, they can not be employed to fabricate fine line circuit boards.